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With a year delay: Intel explains details of HASWELL technology

2014-03-21  |  Comebuy News

Intel has delivered information about its HASWELL-processors, which held it back at its launch last year. On the International Solid-State Circuits Conference (ISSCC) in San Francisco, the manufacturer in various presentations gave a preview on new chip technology and unveiled at the same time unknown details about HASWELL CPUs.

The previously omitted details concerned above all the sizes, transistor numbers, and the interface between HASWELL and optional embedded DRAM. In the introduction, Intel called such details only for single CPUs, now followed information from the minimum to maximum HASWELL configurations. AnandTech clearly summarised it in a table. It expected high additional 300 million transistors for a HASWELL-core, so that the configuration ULT2 + 2 on a total of about one billion transistors running out.

There were also additional information design and configuration of Crystal well (embedded DRAM). The eDRAM works with a clock speed of 1.6 GHz and an operating voltage of 1 volt. It connects to an on package IO (OPIO), capable of transmitting data at speeds up to 6.4 GT/s.

More details concerning especially electricity saving measures at HASWELL such as changes to the memory interface, which reduce Ivy bridge by a factor of 100 settled the leakage compared to its predecessor. The voltage converter FIVR integrated in the chip housing contributed to the increased efficiency full (full integrated voltage regulator) - for Intel ISSCC documents he causes a 90 percent efficiency. Within only 0.32 microseconds he can into the sleep mode switch or leave him, and he accelerated to Turbo frequency in 0.1 microsecond - also contributes further to save electricity.

[with material from]

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